1. Field of the Invention
The present invention relates to a method for manufacturing electrically erasable and programmable read-only memory cells, technically known as EEPROMs, with a single polysilicon level.
2. Discussion of the Related Art
Voltages between 12 volts and 18 volts are conventionally used in the programming of devices with electrically erasable and programmable read-only memory cells, or EEPROMs; this acronym is used hereinafter for the sake of simplicity.
One of the most severe problems of these devices is the need to control and handle the programming and operation voltages, which have a rather high modulus, inside the device itself. In particular, it should be noted that it is the transistors of the EEPROM cell that must be able to ensure its reliability with regard to the programming and operating voltages.
Furthermore, the punch-through or breakdown voltage of the junctions and the threshold voltages of the parasitic field transistors, which are usually present in semiconductor devices, must be higher than the maximum cell programming voltage, with a certain safety voltage range.
These problems and inconveniences become very important with high- and very high-density technologies, which entail thinner oxide layers with more heavily doped substrates.
A typical EEPROM cell, considered herein, is one with a floating gate terminal, disclosed in U.S. Pat. No. 5,107,461. An EEPROM cell is programmed by means of the electron tunneling effect in the thin oxide region, which region has a thickness of 10 nanometers or less, between the drain terminal of the cell and the floating gate terminal.
Cell writing occurs by connecting the control gate terminal of the cell to ground while the drain terminal of the cell is connected to the above-mentioned high programming voltage by means of an access transistor.
Cell erasure occurs by connecting the drain terminal of the cell to the ground while the gate terminal is connected to the high programming voltage. The electrons flow together from the drain terminal to the floating gate terminal, and the sensing transistor, when at the end of the electron pulse, is in the inactive or "off" state.
In known cells, the floating gate terminal is subjected to the heavy implantation of the source and drain terminals, and this fact causes damage to the thin oxide, due to an electrostatic effect, as mentioned in the article "EFFECTS OF ION IMPLANTATION ON DEEP-SUBMICROMETER, DRAIN-ENGINEERED MOSFET TECHNOLOGIES", by Mark G. Stinson and Carlton M. Osburn, published in IEEE TRANSACTIONS ON ELECTRONIC DEVICES, vol. 38, no. 3, March 1991.